VHDL-2008: Just the New StuffElsevier, 26 nov 2007 - 256 pagina's VHDL-2008: Just the New Stuff, as its title says, introduces the new features added to the latest revision of the IEEE standard for the VHDL hardware description language. Written by the Chair and Technical Editor of the IEEE working group, the book is an authoritative guide to how the new features work and how to use them to improve design productivity. It will be invaluable for early adopters of the new language version, for tool implementers, and for those just curious about where VHDL is headed. * First in the market describing the new features of VHDL 2008;* Just the new features, so existing users and implementers can focus on what's new; * Helps readers to learn the new features soon, rather than waiting for new editions of complete VHDL reference books. * Authoritative, written by experts in the area; * Tutorial style, making it more accessible than the VHDL Standard Language Reference Manual. |
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Pagina v
... Type System Changes 103 3.1 Unconstrained Element Types 103 3.1.1 Composite Types 103 3.1.2 Subtype Indications and Constraints 107 3.1.3 Use of Composite Subtypes 109 Variable and Signal Declarations 110 Constant Declarations 110 ...
... Type System Changes 103 3.1 Unconstrained Element Types 103 3.1.1 Composite Types 103 3.1.2 Subtype Indications and Constraints 107 3.1.3 Use of Composite Subtypes 109 Variable and Signal Declarations 110 Constant Declarations 110 ...
Pagina 3
... element or an attribute. Moreover, it can only be used as the type of an explicitly declared constant or a signal (including a port) if the actual type is not an access ... type to declare a formal generic constant, and 1.1 Generic Types 3.
... element or an attribute. Moreover, it can only be used as the type of an explicitly declared constant or a signal (including a port) if the actual type is not an access ... type to declare a formal generic constant, and 1.1 Generic Types 3.
Pagina 6
... type being explicitly specified. Generic. Lists. in. Packages. One of the new places in which we can write generic lists in VHDL-2008 is in package declarations. A ... element type; Chapter 1 — Enhanced Generics 1.2 Generic Lists in Packages.
... type being explicitly specified. Generic. Lists. in. Packages. One of the new places in which we can write generic lists in VHDL-2008 is in package declarations. A ... element type; Chapter 1 — Enhanced Generics 1.2 Generic Lists in Packages.
Pagina 7
... element type; type stack_type is record SP : integer range 0 to size-1; store : stack_array; end record stack_type; procedure push (s : inout stack_type; e : in element type); procedure pop (s : inout stack_type; e : out element type); ...
... element type; type stack_type is record SP : integer range 0 to size-1; store : stack_array; end record stack_type; procedure push (s : inout stack_type; e : in element type); procedure pop (s : inout stack_type; e : out element type); ...
Pagina 8
... element type => unsigned (23 downto 0) ); package operand_stacks is new work. generic_stacks generic map ( size => 16, element type => real ); If we then wrote a use clause in a design unit: use work. address_stacks. all , work ...
... element type => unsigned (23 downto 0) ); package operand_stacks is new work. generic_stacks generic map ( size => 16, element type => real ); If we then wrote a use clause in a design unit: use work. address_stacks. all , work ...
Inhoudsopgave
| 1 | |
Chapter 2 Other Major Features | 53 |
Chapter 3 Type System Changes | 103 |
Chapter 4 New and Changed Operations | 127 |
Chapter 5 New and Changed Statements | 143 |
Chapter 6 Modeling Enhancements | 159 |
Chapter 7 Improved IO | 169 |
Chapter 8 Standard Packages | 179 |
Chapter 9 Miscellaneous Changes | 207 |
Chapter 10 Whats Next | 229 |
Index | 237 |
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Accellera address_type alias array type attribute begin bit vector boolean cipher component configuration constant context declaration conversion functions decryption denorm design unit digest digital envelope digital signature directive downto earlier versions element subtype element type encoded encryption envelope encryption tool end entity end package end record entity and architecture example expression external name fixed-point float floating-point formal generic type fully constrained hash function hexadecimal identifier IEEE index range inout instance instantiate integer IP provider numeric_bit numeric_std NumericarrayType object octal operand operations Overflow round overloaded package body package defines Param parameter pathname port map predefined protect protect protect protected type pure function radix point result session key sfixed shared variable signed specify sta_logic statement std logic vector std ulogic vector string subprogram testbench textio tion type conversion ufixed unconstrained uninstantiated package unsigned versions of VHDL VHPI write Xmap