VHDL-2008: Just the New StuffElsevier, 26 nov 2007 - 256 pagina's VHDL-2008: Just the New Stuff, as its title says, introduces the new features added to the latest revision of the IEEE standard for the VHDL hardware description language. Written by the Chair and Technical Editor of the IEEE working group, the book is an authoritative guide to how the new features work and how to use them to improve design productivity. It will be invaluable for early adopters of the new language version, for tool implementers, and for those just curious about where VHDL is headed. * First in the market describing the new features of VHDL 2008;* Just the new features, so existing users and implementers can focus on what's new; * Helps readers to learn the new features soon, rather than waiting for new editions of complete VHDL reference books. * Authoritative, written by experts in the area; * Tutorial style, making it more accessible than the VHDL Standard Language Reference Manual. |
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Pagina 2
... downto 0); pkt_type : bit vector (2 downto 0); length : unsigned (4 downto 0); payload : byte_vector (0 to 31); checksum : unsigned (7 downto 0); end record msg_packet; signal pkt_sel : bit; signal pkt_in1, pkt in2, pkt_out : msg_pkt ...
... downto 0); pkt_type : bit vector (2 downto 0); length : unsigned (4 downto 0); payload : byte_vector (0 to 31); checksum : unsigned (7 downto 0); end record msg_packet; signal pkt_sel : bit; signal pkt_in1, pkt in2, pkt_out : msg_pkt ...
Pagina 4
... downto 0), init_val => "ZZZZ" ); We can also use this technique to provide values for initializing variables and signals declared to be of the formal generic type. Note that the generic list in this entity makes use of one generic (T) ...
... downto 0), init_val => "ZZZZ" ); We can also use this technique to provide values for initializing variables and signals declared to be of the formal generic type. Note that the generic list in this entity makes use of one generic (T) ...
Pagina 8
... downto 0) ); If we analyze this instantiation into our working library, we can refer to it in other design units, for example: architecture behavior of CPU is use work. address_stacks. all ; begin interpret_instructions : process is ...
... downto 0) ); If we analyze this instantiation into our working library, we can refer to it in other design units, for example: architecture behavior of CPU is use work. address_stacks. all ; begin interpret_instructions : process is ...
Pagina 9
... downto 0); variable FP_operand_stack : operand_stacks. Stack; variable TOS operand : real ; address_stacks. push (return address_stack, PC); operand_stacks. pop (FP operand_stack, TOS operand); An important aspect of VHDL's strong ...
... downto 0); variable FP_operand_stack : operand_stacks. Stack; variable TOS operand : real ; address_stacks. push (return address_stack, PC); operand_stacks. pop (FP operand_stack, TOS operand); An important aspect of VHDL's strong ...
Pagina 14
... downto 0) ); package real_wrappers is new ID_wrappers generic map ( test case type => real ); variable next word test : word wrappers. wrapped test case; variable next real_test : real_wrappers. wrapped test case; begin next word test ...
... downto 0) ); package real_wrappers is new ID_wrappers generic map ( test case type => real ); variable next word test : word wrappers. wrapped test case; variable next real_test : real_wrappers. wrapped test case; begin next word test ...
Inhoudsopgave
| 1 | |
Chapter 2 Other Major Features | 53 |
Chapter 3 Type System Changes | 103 |
Chapter 4 New and Changed Operations | 127 |
Chapter 5 New and Changed Statements | 143 |
Chapter 6 Modeling Enhancements | 159 |
Chapter 7 Improved IO | 169 |
Chapter 8 Standard Packages | 179 |
Chapter 9 Miscellaneous Changes | 207 |
Chapter 10 Whats Next | 229 |
Index | 237 |
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Accellera address_type alias array type attribute begin bit vector boolean cipher component configuration constant context declaration conversion functions decryption denorm design unit digest digital envelope digital signature directive downto earlier versions element subtype element type encoded encryption envelope encryption tool end entity end package end record entity and architecture example expression external name fixed-point float floating-point formal generic type fully constrained hash function hexadecimal identifier IEEE index range inout instance instantiate integer IP provider numeric_bit numeric_std NumericarrayType object octal operand operations Overflow round overloaded package body package defines Param parameter pathname port map predefined protect protect protect protected type pure function radix point result session key sfixed shared variable signed specify sta_logic statement std logic vector std ulogic vector string subprogram testbench textio tion type conversion ufixed unconstrained uninstantiated package unsigned versions of VHDL VHPI write Xmap