VHDL-2008: Just the New StuffElsevier, 26 nov 2007 - 256 pagina's VHDL-2008: Just the New Stuff, as its title says, introduces the new features added to the latest revision of the IEEE standard for the VHDL hardware description language. Written by the Chair and Technical Editor of the IEEE working group, the book is an authoritative guide to how the new features work and how to use them to improve design productivity. It will be invaluable for early adopters of the new language version, for tool implementers, and for those just curious about where VHDL is headed.* First in the market describing the new features of VHDL 2008;* Just the new features, so existing users and implementers can focus on what's new; * Helps readers to learn the new features soon, rather than waiting for new editions of complete VHDL reference books. * Authoritative, written by experts in the area; * Tutorial style, making it more accessible than the VHDL Standard Language Reference Manual. |
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Pagina v
... Attribute Specifications 111 Allocated Objects 111 Interface Objects 112 Summary : Determining Array Index Ranges 117 Type Conversions 118 Alias Declarations and Subtype Attributes 119 Resolved Composite Subtypes 122 103 3.2 Resolved ...
... Attribute Specifications 111 Allocated Objects 111 Interface Objects 112 Summary : Determining Array Index Ranges 117 Type Conversions 118 Alias Declarations and Subtype Attributes 119 Resolved Composite Subtypes 122 103 3.2 Resolved ...
Pagina vii
... Attribute Specifications in Package Bodies 219 9.14 Attribute Specification for Overloaded Subprograms 219 9.15 Integer Expressions in Range Bounds 220 9.16 Action on Assertion Violations 221 9.17 ' Path_Name and ' Instance_Name 221 ...
... Attribute Specifications in Package Bodies 219 9.14 Attribute Specification for Overloaded Subprograms 219 9.15 Integer Expressions in Range Bounds 220 9.16 Action on Assertion Violations 221 9.17 ' Path_Name and ' Instance_Name 221 ...
Pagina 1
... . This can take the form of a type name , a type name followed by a constraint , or a subtype attribute . EXAMPLE 1.1 A generic multiplexer A multiplexer selects between two. 1 Chapter 1. Enhanced Generics 1.1 Generic Types.
... . This can take the form of a type name , a type name followed by a constraint , or a subtype attribute . EXAMPLE 1.1 A generic multiplexer A multiplexer selects between two. 1 Chapter 1. Enhanced Generics 1.1 Generic Types.
Pagina 3
... attribute . Moreover , it can only be used as the type of an explicitly declared constant or a signal ( including a port ) if the actual type is not an access type and does not contain a subelement of an access type . For signals , the ...
... attribute . Moreover , it can only be used as the type of an explicitly declared constant or a signal ( including a port ) if the actual type is not an access type and does not contain a subelement of an access type . For signals , the ...
Pagina 4
... attributes . This may at first seem an onerous restriction , but it does mean that a VHDL analyzer can check the entity and architecture for correctness in isolation , independently of any particular instantiation . It also means we don ...
... attributes . This may at first seem an onerous restriction , but it does mean that a VHDL analyzer can check the entity and architecture for correctness in isolation , independently of any particular instantiation . It also means we don ...
Inhoudsopgave
| 1 | |
Chapter 2 Other Major Features | 53 |
Chapter 3 Type System Changes | 103 |
Chapter 4 New and Changed Operations | 127 |
Chapter 5 New and Changed Statements | 143 |
Chapter 6 Modeling Enhancements | 159 |
Chapter 7 Improved IO | 169 |
Chapter 8 Standard Packages | 179 |
Chapter 9 Miscellaneous Changes | 207 |
Chapter 10 Whats Next | 229 |
Index | 237 |
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Accellera alias array type attribute begin bit_vector boolean component configuration constant context declaration conversion functions decryption denorm design unit digital envelope digital signature directive downto earlier versions element subtype element_type encoded encryption envelope encryption tool end architecture RTL end entity end function end package end procedure end process end record entity and architecture example expression external name fixed-point floating-point formal generic package formal generic type fully constrained hash function hexadecimal identifier index range index subtype inout instance instantiate integer IP provider numeric_bit numeric_std NumericArrayType object octal operand operations overflow round package body package defines Param pathname port map predefined protected type pure function radix point result Section session key sfixed shared variable size_res specify statement std_logic std_logic_1164 std_logic_vector std_ulogic string string literal subprogram testbench tion to_string type conversion ufixed unconstrained uninstantiated package vector versions of VHDL VHPI write xmap