Design Methodologies for VLSI CircuitsPaul G. Jespers, C.H. Sequin, F. van de Wiele Springer Science & Business Media, 28 feb 1982 - 456 pagina's |
Inhoudsopgave
TRENDS IN VERY LARGE SCALE INTEGRATION AND THEIR IMPACT ON THE DESIGNER | 1 |
TECHNOLOGICAL PROCESSES FOR VLSI | 11 |
MODELS FOR MOS TRANSISTORS | 55 |
Data Path and Finite State Machines | 73 |
CIF Library Starting Frames and Scalable Design Rules | 109 |
STANDARD INTERCHANGE FORMATS FOR INTEGRATED CIRCUIT DESIGN | 139 |
COMPUTER AIDED DESIGN TECHNIQUES FOR VLSI | 173 |
RELIABILITY IMPROVEMENT IN MANUAL LAYOUT DESIGN | 227 |
A VLSI CHIP ASSEMBLER | 329 |
A SINGLECHIP FLOATINGPOINT PROCESSOR A Case Study in Structured Design | 357 |
GENERAL PURPOSE VLSI COMPONENTS FOR DISTRIBUTED COMPUTING SYSTEMS | 375 |
ARCHITECTURES FOR MULTIPROCESSOR SYSTEMS ARRAY SYSTEM VERSUS FUNCTIONAL DECOMPOSED SYSTEMS | 393 |
ANALOG TECHNIQUES USING VLSI TECHNOLOGY | 413 |
VLSI TECHNOLOGY IMPLICATIONS FOR SIGNAL PROCESSING | 433 |
PARTICIPANTS | 453 |
LECTURERS | 455 |
DESIGN FOR TESTABILITY | 249 |
VLSI AID PETRI NETS | 285 |
ARCHITECTURE AND DESIGN OF VON NEUMANN MICROPROCESSORS | 301 |
SCIENTIFIC ORGANIZING COMMITTEE | 456 |
Veelvoorkomende woorden en zinsdelen
algorithms analog analog circuits array automated byte capacitances capacitor cell definition channel chip area chip assembler circuit simulation clock complexity components connection cost datapath decoder defined density design rule checking design rules devices diagram EDIFF electron elements etching example fabrication fault Figure filters finite state machines flipflops format gate geometrical hardware hierarchical IEEE implementation increased input integrated circuits interconnection interface language layer layout design lines lithography logic simulation mask layout memory microcode microprocessor modules MOS technology MOS transistor multiplexer node operation output oxide parameters path pattern Petri Net PLA's polysilicon possible problem Proc processor register transfer level representation routing scan-path sequence SEQUIN shift register silicon specified standard cell STIF substrate switching techniques terminal testability tion VLSI design voltage wafer Xerox PARC